1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to forming uniform metal interconnections for semiconductor integrated circuits to eliminate metal line sheet resistance variations.
2. Background Description
A semiconductor chip is an array of devices with conducting terminals that are interconnected by wiring patterns of metal strips. In Very Large Scale Integration (VLSI) chips, these metal wiring patterns are multilayered. Each wiring layer is separated from other conducting layers by insulating material layers. Interconnections between different wiring pattern layers are made through holes (vias) that are etched through the insulating material layers.
As VLSI chip features shrink and the number of wiring layers increases, surface irregularities in each layer translate to subsequent layers, making each subsequent layer's surface even more irregular. These irregularities distort shapes formed on the surface, making level to level alignment difficult. In some cases, this distortion is so severe as to make it nearly impossible to adequately replicate (print) the intended shape or to align printing masks to previous levels.
One prior art way surface irregularities were reduced was filling the vias with conducting material (i.e., form studs in the vias) before printing the wiring pattern on the insulating material surface. However, the raised wiring layer shapes on the surface still caused irregularities in subsequent surfaces. Therefore, techniques have been developed that are used at various levels to create a nearly perfectly flat, or, planar surface at each layer, so that shapes are printed with high dimensional and geometric accuracy. These techniques are known in the art as planarization techniques. One such planarization process is known as Chemical-Mechanical Polishing, also known as Chem-Mech Polishing or CMP.
A CMP application known as the Damascene process provides a planar wiring layer surface by forming trenches in the surface and forming wires in the trenches. A layer of SiO.sub.2 or another suitable dielectric is planarized by CMP and wiring patterns are formed as recesses or trenches in the planar surface. Then, after a conformal metal deposition, the metal surface is chem-mech polished to selectively remove metal until metal conductor remains only in the patterned recesses of the dielectric. The metal is completely removed from the dielectric surface in non-recessed areas.
Presently, the Damascene process is used, when possible, to produce lines and vias for intra-chip wiring. The uniformity of lines formed by a damascene process depends upon the uniformity of the trenches in which the lines are formed. Unfortunately, oxide trench etching in damascene line formation is not perfectly uniform and so trench variations result across the wafer. Trench depth variation causes a wide metal sheet resistance variation across the wafer. Trench width variation also results in an overall chip yield decrease due to line to line shorts at one extreme and open lines at the other.
Thus, there is a need for a damascene process with reduced oxide trench variation, metal line sheet resistance variation and yield loss.